// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
/*
 * Copyright (C) 2023 rengaomin@allwinnertech.com
 */

#ifndef _DT_BINDINGS_CLK_SUN60IW2_H_
#define _DT_BINDINGS_CLK_SUN60IW2_H_

#define CLK_REFPLL		0
#define CLK_DDRPLL		1
#define CLK_PLL_PERI0		2
#define CLK_PLL_PERI0_2X	3
#define CLK_PERI0_DIV3		4
#define CLK_PLL_PERI0_800M	5
#define CLK_PLL_PERI0_480M	6
#define CLK_PLL_PERI0_600M	7
#define CLK_PLL_PERI0_400M	8
#define CLK_PLL_PERI0_300M	9
#define CLK_PLL_PERI0_200M	10
#define CLK_PLL_PERI0_160M	11
#define CLK_PLL_PERI0_150M	12
#define CLK_PLL_PERI1		13
#define CLK_PLL_PERI1_2X	14
#define CLK_PLL_PERI1_800M	15
#define CLK_PLL_PERI1_480M	16
#define CLK_PLL_PERI1_600M	17
#define CLK_PLL_PERI1_400M	18
#define CLK_PLL_PERI1_300M	19
#define CLK_PLL_PERI1_200M	20
#define CLK_PLL_PERI1_160M	21
#define CLK_PLL_PERI1_150M	22
#define CLK_GPU0PLL		23
#define CLK_VIDEO0PLL4X		24
#define CLK_VIDEO0PLL3X		25
#define CLK_VIDEO1PLL4X		26
#define CLK_VIDEO2PLL4X		27
#define CLK_VE0PLL		28
#define CLK_VE1PLL		29
#define CLK_AUDIO0PLL4X		30
#define CLK_AUDIO1PLL_DIV2	31
#define CLK_NPUPLL		32
#define CLK_DEPLL4X		33
#define CLK_AHB			34
#define CLK_APB0		35
#define CLK_APB1		36
#define CLK_TRACE		37
#define CLK_GIC			38
#define CLK_CPU_PERI		39
#define CLK_ITS_PCIE0_ACLK	40
#define CLK_ITS_PCIE0_HCLK	41
#define CLK_NSI			42
#define CLK_NSI_CFG		43
#define CLK_MBUS		44
#define CLK_IOMMU0_SYS_HCLK	45
#define CLK_IOMMU0_SYS_PCLK	46
#define CLK_IOMMU0_SYS_MCLK	47
#define CLK_MSI_LITE0		48
#define CLK_MSI_LITE1		49
#define CLK_MSI_LITE2		50
#define CLK_IOMMU1_SYS_HCLK	51
#define CLK_IOMMU1_SYS_PCLK	52
#define CLK_IOMMU1_SYS_MCLK	53
#define CLK_CPUS_HCLK_GATE	54
#define CLK_STORE_AHB_GATE	55
#define CLK_MSILITE0_AHB_GATE	56
#define CLK_USB_SYS_AHB_GATE	57
#define CLK_SERDES_AHB_GATE	58
#define CLK_GPU0_AHB_GATE	59
#define CLK_NPU_AHB_GATE	60
#define CLK_DE_AHB_GATE		61
#define CLK_VID_OUT1_AHB_GATE	62
#define CLK_VID_OUT0_AHB_GATE	63
#define CLK_VID_IN_AHB_GATE	64
#define CLK_VE_AHB_GATE		65
#define CLK_MSILITE2_MBUS_GATE	66
#define CLK_STORE_MBUS_GATE	67
#define CLK_MSILITE0_MBUS_GATE	68
#define CLK_SERDES_MBUS_GATE	69
#define CLK_VID_IN_MBUS_GATE	70
#define CLK_NPU_MBUS_GATE	71
#define CLK_GPU0_MBUS_GATE	72
#define CLK_VE_MBUS_GATE	73
#define CLK_DESYS_MBUS_GATE	74
#define CLK_GMAC1_MBUS		75
#define CLK_GMAC0_MBUS		76
#define CLK_ISP_MBUS		77
#define CLK_CSI_MBUS		78
#define CLK_NAND_MBUS		79
#define CLK_DMA1_MBUS		80
#define CLK_CE_MBUS		81
#define CLK_VE_MBUS		82
#define CLK_DMA0_MBUS		83
#define CLK_DMA0_BUS		84
#define CLK_DMA1_BUS		85
#define CLK_SPINLOCK		86
#define CLK_MSGBOX0		87
#define CLK_PWM0		88
#define CLK_PWM1		89
#define CLK_DBGSYS		90
#define CLK_SYSDAP		91
#define CLK_TIMER0_CLK0		92
#define CLK_TIMER0_CLK1		93
#define CLK_TIMER0_CLK2		94
#define CLK_TIMER0_CLK3		95
#define CLK_TIMER0_CLK4		96
#define CLK_TIMER0_CLK5		97
#define CLK_TIMER0_CLK6		98
#define CLK_TIMER0_CLK7		99
#define CLK_TIMER0_CLK8		100
#define CLK_TIMER0_CLK9		101
#define CLK_TIMER0		102
#define CLK_AVS			103
#define CLK_DE0			104
#define CLK_BUS_DE0		105
#define CLK_DI			106
#define CLK_BUS_DI		107
#define CLK_G2D			108
#define CLK_BUS_G2D		109
#define CLK_EINK		110
#define CLK_EINK_PANEL		111
#define CLK_BUS_EINK		112
#define CLK_VE_ENC0		113
#define CLK_VE_DEC		114
#define CLK_BUS_VE_DEC		115
#define CLK_BUS_VE_ENC		116
#define CLK_CE			117
#define CLK_CE_SYS		118
#define CLK_BUS_CE		119
#define CLK_NPU			120
#define CLK_BUS_NPU		121
#define CLK_GPU0		122
#define CLK_BUS_GPU0		123
#define CLK_DRAM0		124
#define CLK_BUS_DRAM0		125
#define CLK_NAND0_CLK0		126
#define CLK_NAND0_CLK1		127
#define CLK_BUS_NAND0		128
#define CLK_SMHC0		129
#define CLK_BUS_SMHC0		130
#define CLK_SMHC1		131
#define CLK_BUS_SMHC1		132
#define CLK_SMHC2		133
#define CLK_BUS_SMHC2		134
#define CLK_SMHC3		135
#define CLK_BUS_SMHC3		136
#define CLK_UFS_AXI		137
#define CLK_UFS_CFG		138
#define CLK_UFS			139
#define CLK_UART0		140
#define CLK_UART1		141
#define CLK_UART2		142
#define CLK_UART3		143
#define CLK_UART4		144
#define CLK_UART5		145
#define CLK_UART6		146
#define CLK_TWI0		147
#define CLK_TWI1		148
#define CLK_TWI2		149
#define CLK_TWI3		150
#define CLK_TWI4		151
#define CLK_TWI5		152
#define CLK_TWI6		153
#define CLK_TWI7		154
#define CLK_TWI8		155
#define CLK_TWI9		156
#define CLK_TWI10		157
#define CLK_TWI11		158
#define CLK_TWI12		159
#define CLK_SPI0		160
#define CLK_BUS_SPI0		161
#define CLK_SPI1		162
#define CLK_BUS_SPI1		163
#define CLK_SPI2		164
#define CLK_BUS_SPI2		165
#define CLK_SPIF		166
#define CLK_BUS_SPIF		167
#define CLK_SPI3		168
#define CLK_BUS_SPI3		169
#define CLK_SPI4		170
#define CLK_BUS_SPI4		171
#define CLK_GPADC0_24M		172
#define CLK_GPADC0		173
#define CLK_THS0		174
#define CLK_IRRX		175
#define CLK_BUS_IRRX		176
#define CLK_IRTX		177
#define CLK_BUS_IRTX		178
#define CLK_LRADC		179
#define CLK_SGPIO		180
#define CLK_BUS_SGPIO		181
#define CLK_LPC			182
#define CLK_BUS_LPC		183
#define CLK_I2SPCM0		184
#define CLK_BUS_I2SPCM0		185
#define CLK_I2SPCM1		186
#define CLK_BUS_I2SPCM1		187
#define CLK_I2SPCM2		188
#define CLK_I2SPCM2_ASRC	189
#define CLK_BUS_I2SPCM2		190
#define CLK_I2SPCM3		191
#define CLK_BUS_I2SPCM3		192
#define CLK_SPDIF_TX		193
#define CLK_SPDIF_RX		194
#define CLK_SPDIF		195
#define CLK_DMIC		196
#define CLK_BUS_DMIC		197
#define CLK_USB			198
#define CLK_USB0_DEVICE		199
#define CLK_USB0_EHCI		200
#define CLK_USB0_OHCI		201
#define CLK_USB1		202
#define CLK_USB1_EHCI		203
#define CLK_USB1_OHCI		204
#define CLK_USB_REF		205
#define CLK_USB2_U2_REF		206
#define CLK_USB2_SUSPEND	207
#define CLK_USB2_MF		208
#define CLK_USB2_U3_UTMI	209
#define CLK_USB2_U2_PIPE	210
#define CLK_PCIE0_AUX		211
#define CLK_PCIE0_AXI_SLV	212
#define CLK_SERDES_PHY_CFG	213
#define CLK_GMAC_PTP		214
#define CLK_GMAC0_PHY		215
#define CLK_GMAC0		216
#define CLK_GMAC1_PHY		217
#define CLK_GMAC1		218
#define CLK_VO0_TCONLCD0	219
#define CLK_BUS_VO0_TCONLCD0	220
#define CLK_VO0_TCONLCD1	221
#define CLK_BUS_VO0_TCONLCD1	222
#define CLK_VO0_TCONLCD2	223
#define CLK_BUS_VO0_TCONLCD2	224
#define CLK_DSI0		225
#define CLK_BUS_DSI0		226
#define CLK_DSI1		227
#define CLK_BUS_DSI1		228
#define CLK_COMBPHY0		229
#define CLK_COMBPHY1		230
#define CLK_TCONTV0		231
#define CLK_TCONTV1		232
#define CLK_EDP_TV		233
#define CLK_EDP			234
#define CLK_HDMI_REF		235
#define CLK_HDMI_TV		236
#define CLK_HDMI		237
#define CLK_HDMI_SFR		238
#define CLK_HDCP_ESM		239
#define CLK_DPSS_TOP0		240
#define CLK_DPSS_TOP1		241
#define CLK_LEDC		242
#define CLK_BUS_LEDC		243
#define CLK_DSC			244
#define CLK_CSI_MASTER0		245
#define CLK_CSI_MASTER1		246
#define CLK_CSI_MASTER2		247
#define CLK_CSI			248
#define CLK_BUS_CSI		249
#define CLK_ISP			250
#define CLK_DDRPLL_GATE		251
#define CLK_DDRPLL_AUTO		252
#define CLK_PERI0_300M_DSP	253
#define CLK_PERI0PLL2X_GATE	254
#define CLK_PERI0_800M_GATE	255
#define CLK_PERI0_600M_GATE	256
#define CLK_PERI0_480M_GATE_ALL	257
#define CLK_PERI0_480M_GATE_SW	258
#define CLK_PERI0_160M_GATE	259
#define CLK_PERI0_300M_GATE	260
#define CLK_PERI0_300M_SW	261
#define CLK_PERI0_150M_GATE	262
#define CLK_PERI0_400M_GATE	263
#define CLK_PERI0_400M_SW	264
#define CLK_PERI0_200M_GATE	265
#define CLK_PERI0PLL2X_AUTO	266
#define CLK_PERI0_800M_AUTO	267
#define CLK_PERI0_600M_AUTO	268
#define CLK_PERI0_480M_AUTO_GATE	269
#define CLK_PERI0_480M_AUTO	270
#define CLK_PERI0_160M_AUTO	271
#define CLK_PERI0_300M_AUTO_GATE	272
#define CLK_PERI0_300M_AUTO	273
#define CLK_PERI0_150M_AUTO	274
#define CLK_PERI0_400M_AUTO_GATE	275
#define CLK_PERI0_400M_AUTO	276
#define CLK_PERI0_200M_AUTO	277
#define CLK_PERI1_300M_DSP	278
#define CLK_PERI1_800M_GATE	279
#define CLK_PERI1_600M_GATE	280
#define CLK_PERI1_600M_SW	281
#define CLK_PERI1_480M_GATE	282
#define CLK_PERI1_480M_SW	283
#define CLK_PERI1_160M_GATE	284
#define CLK_PERI1_300M_GATE	285
#define CLK_PERI1_300M_SW	286
#define CLK_PERI1_150M_GATE	287
#define CLK_PERI1_400M_GATE	288
#define CLK_PERI1_400M_SW	289
#define CLK_PERI1_200M_GATE	290
#define CLK_PERI1_800M_AUTO	291
#define CLK_PERI1_600M_AUTO_GATE	292
#define CLK_PERI1_600M_AUTO	293
#define CLK_PERI1_480M_AUTO_GATE	294
#define CLK_PERI1_480M_AUTO	295
#define CLK_PERI1_160M_AUTO	296
#define CLK_PERI1_300M_AUTO_GATE	297
#define CLK_PERI1_300M_AUTO	298
#define CLK_PERI1_150M_AUTO	299
#define CLK_PERI1_400M_AUTO_GATE	300
#define CLK_PERI1_400M_AUTO	301
#define CLK_PERI1_200M_AUTO	302
#define CLK_VIDEO2PLL3X_GATE	303
#define CLK_VIDEO1PLL3X_GATE	304
#define CLK_VIDEO0PLL3X_GATE	305
#define CLK_VIDEO2PLL4X_GATE	306
#define CLK_VIDEO1PLL4X_GATE	307
#define CLK_VIDEO0PLL4X_GATE	308
#define CLK_VIDEO2PLL3X_AUTO	309
#define CLK_VIDEO1PLL3X_AUTO	310
#define CLK_VIDEO0PLL3X_AUTO	311
#define CLK_VIDEO2PLL4X_AUTO	312
#define CLK_VIDEO1PLL4X_AUTO	313
#define CLK_VIDEO0PLL4X_AUTO	314
#define CLK_GPU0PLL_GATE	315
#define CLK_GPU0PLL_AUTO	316
#define CLK_VE1PLL_GATE		317
#define CLK_VE0PLL_GATE		318
#define CLK_VE1PLL_AUTO		319
#define CLK_VE0PLL_AUTO		320
#define CLK_AUDIO1PLL_DIV5_GATE	321
#define CLK_AUDIO1PLL_DIV2_GATE	322
#define CLK_AUDIO0PLL4X_GATE	323
#define CLK_AUDIO1PLL_DIV5_AUTO	324
#define CLK_AUDIO1PLL_DIV2_AUTO	325
#define CLK_AUDIO0PLL4X_AUTO	326
#define CLK_NPUPLL_GATE		327
#define CLK_NPUPLL_AUTO		328
#define CLK_DEPLL3X_GATE	329
#define CLK_DEPLL4X_GATE	330
#define CLK_DEPLL3X_AUTO	331
#define CLK_DEPLL4X_AUTO	332
#define CLK_DDRPLL_STAT		333
#define CLK_PERI0PLL2X_STAT	334
#define CLK_PERI0_800M_STAT	335
#define CLK_PERI0_600M_STAT	336
#define CLK_PERI0_480M_GATE_A	337
#define CLK_PERI0_480M_STAT	338
#define CLK_PERI0_160M_STAT	339
#define CLK_PERI0_300M_GATE_A	340
#define CLK_PERI0_300M_STAT	341
#define CLK_PERI0_150M_STAT	342
#define CLK_PERI0_400M_GATE_A	343
#define CLK_PERI0_400M_STATUS	344
#define CLK_PERI0_200M_STAT	345
#define CLK_PERI1_800M_STAT	346
#define CLK_PERI1_600M_GATE_A	347
#define CLK_PERI1_600M_STAT	348
#define CLK_PERI1_480M_GATE_A	349
#define CLK_PERI1_480M_STAT	350
#define CLK_PERI1_160M_STAT	351
#define CLK_PERI1_300M_GATE_A	352
#define CLK_PERI1_300M_STAT	353
#define CLK_PERI1_150M_STAT	354
#define CLK_PERI1_400M_GATE_A	355
#define CLK_PERI1_400M_STAT	356
#define CLK_PERI1_200M_STAT	357
#define CLK_VIDEO2PLL3X_STAT	358
#define CLK_VIDEO1PLL3X_STAT	359
#define CLK_VIDEO0PLL3X_STAT	360
#define CLK_VIDEO2PLL4X_STAT	361
#define CLK_VIDEO1PLL4X_STAT	362
#define CLK_VIDEO0PLL4X_STAT	363
#define CLK_GPU0PLL_STAT	364
#define CLK_VE1PLL_STAT		365
#define CLK_VE0PLL_STAT		366
#define CLK_AUDIO1PLL_DIV5_STAT	367
#define CLK_AUDIO1PLL_DIV2_STAT	368
#define CLK_AUDIO0PLL4X_STAT	369
#define CLK_NPUPLL_STAT		370
#define CLK_DEPLL3X_STAT	371
#define CLK_DEPLL4X_STAT	372
#define CLK_RES_DCAP_24M	373
#define CLK_APB2JTAG		374

#define CLK_MAX_NO	(CLK_APB2JTAG + 1)

#endif /* _DT_BINDINGS_CLK_SUN60IW2_H_ */
